1. The Field of the Invention
The field of the invention relates to computer and communication systems having a host system interfacing with support or peripheral modules for performing digital signal processing functions. More specifically, the present invention relates to the minimization of hardware components in computer architectures within peripheral modules. More particularly, the invention relates to independent caching of instructions and/or data from a shared host memory.
2. Present State of the Art
Computer systems originally were self-reliant in performing both computational and peripheral functions. Computer systems processed data as well as generated control signals and performed calculations for causing peripheral modules to react as directed. As peripheral functions, such as digital signal processing, increased in complexity, computer systems became largely distracted from their own computational role by the required burden of providing computational support and control functions to peripheral modules. To combat this problem, peripheral modules were designed with additional sophistication.
Modern peripheral modules such as digital signal processing modules and other devices incorporate many of the attributes of computer systems themselves. For example, peripheral modules incorporate digital signal processors and on-board memory devices such as ROMs and RAMs. Such configured peripheral modules became autonomous yet focused in carrying out a specific objective such as filtering and conditioning signals, generating waveforms, and other functions.
Although these modem systems perform focused, independent, digital signal processing functions, such peripheral modules still rely on a computer system or a host system to provide control, data, or information for processing. For example, peripheral modules having a digital signal processor may rely upon a host computer to generate control signals or deliver data for encoding or modulating.
To facilitate the transfer of data between a host system and a peripheral system, interface standards have been established. Both a host system and a peripheral module incorporate these standards into their interfaces for compliant interaction therebetween. Such peripheral modules electrically connect to the host system according to a defined interface. Such interfaces include parallel and serial interfaces and take specific forms such as Universal Serial Bus (USB), PCMCIA, as well as other interface standards.
Peripheral modules taking the form of extended processing systems such as modems, traditionally operate as dedicated systems having resident processing and memory resources. Additionally, peripheral modules may couple to a host system bus through a bus interface unit that provides a compatible loading and electrical interface with the host bus. Traditional host bus configurations subordinate peripheral modules to host processor control (ie., the host processor operates as the host bus master while interfacing with peripheral modules). Peripheral modules requesting access to the host bus must initially assert this request in a form such as a direct memory access (DMA) request.
Traditionally, such a master/slave interface between a peripheral module and host bus have been impractical for continuous and substantial transfer of information due to bus architectures and disparate performance of digital signal processor and host system resources. For example, a peripheral module having a digital signal processor may be operating on 10 nanosecond clock rates while host system resources such as memory may only be capable of functioning at access rates on the order of 100 nanoseconds. Because of such a throughput disparity, peripheral modules were required to incorporate their own support resources such as memory devices onto a bus local to the peripheral module. Such a peripheral-resident bus incorporated data and program storage for use by the peripheral module. Incorporation of additional program and data storage (e.g., ROM and RAM) onto a peripheral module significantly increases the cost of the peripheral module.
In addition to the increased cost of a peripheral module, replication of existing types of resources (e.g., ROM and RAM) on the peripheral module increases the overall "footprint" (i.e., the necessary area for routing and placement of components) of the peripheral module. FIG. 1 represents a prior art configuration of a host system 100 comprising a host processor 102 operably coupled to a ROM 106 and RAM 108. ROM 106 provides program instructions and data to host processor 102 via host bus 104. RAM 108 also provides instructions and data to host processor 102 via host bus 104.
Optional configurations of host processor system 100 also comprise a caching configuration for improved efficiency of host processor 102 through pre-fetching instructions and data. Such configurations employ a cache controller 110 operably coupled to host bus 104 for pre-fetching instructions and data for storage in a high speed memory device such as a cache 112. Cache 112 operably couples to host processor 102 through cache controller 110 and a host cache bus 114.
Still referring to FIG. 1, prior art configurations of host systems 100 optionally comprise a bus interface unit (BIU) 116 operably coupled to host bus 104. BIU 116 provides operable coupling of a peripheral module 118 to interface with host system 100. Alternative prior art embodiments have physically placed BIU 116 within peripheral module 118 or required a mating bus interface module on both the host side of the interface and the peripheral side of the interface. Regardless of the actual location of BIU 116, both configurations perform similarly by accommodating interaction between master-configured host system 100 and slave-configured peripheral module 118.
By way of example, peripheral module 118 comprises a digital signal processor 120 operably coupled to a dedicated peripheral ROM 122 and peripheral RAM 124 through an independent peripheral bus 126. Peripheral ROM 122 and peripheral RAM 124 have comprised program instructions and data specific to the operation of digital signal processor 120. Because of the inherent computation-intensive and/or continuous processing of digital signal processor 120, accessible and available storage for digital signal processor 120 is desirable. Slave-configured peripheral module 118, in prior art configurations, is unable to maintain sufficient information exchange rates with host system 100 for providing instructions and data due to bus architectures and disparate performance of digital signal processor and host system resources. Thus, prior art configurations have required dedicated resident storage devices sufficiently sized for autonomous program and data storage and retrieval to be collocated with digital signal processor 120.
In conclusion, there exists a need for an apparatus and a method of providing instructions and/or data to a digital signal processor in a peripheral module without requiring substantial resident dedicated storage in the peripheral module.